Emitter-coupled logic circuits generally operate by switching currents between two parallel current paths. A switching transistor is connected in each of the parallel paths, and the emitters of the transistors are coupled together. A basic current-mode logic (CML) switch 10 is illustrated in FIG. 1. The switch is connected between a positive supply voltage V.sub.CC and a negative supply voltage V.sub.EE. A current source CS supplies a constant current I.sub.S. In the normal arrangement, V.sub.BB is a reference voltage which is applied to the base of a transistor Q2 and the input voltage V.sub.IN is applied to the base of a transistor Q1. V.sub.BB is set at a point halfway between the high and low states of the input voltage V.sub.IN. Thus, when V.sub.IN is high, transistor Q1 conducts and a voltage drop across a load resistor R1 causes the output V.sub.C1 to go low. Conversely, when V.sub.IN is low, transistor Q2 conducts and the output voltage V.sub.C1 goes high.
The output voltage V.sub.C2 is the inverse of V.sub.C1. That is, when V.sub.IN is high, the output V.sub.C2 is high; when V.sub.IN is low, the output V.sub.C2 is low.
The minimum voltage swing between the high and low states of V.sub.IN necessary to switch the current completely between transistors Q1 and Q2 is about 250 mV, centered about V.sub.BB. Alternatively, transistors Q1 and Q2 can be driven differentially with a smaller voltage swing (e.g., 150 mV). Normally, the input signal swing is made considerably larger (approximately 600-750 mV for a single-ended input and 300-350 mV for differential inputs) to provide noise immunity and to allow for variations in the output voltage levels in the CML switches connected into a given logic network. In FIG. 1, VC1 ranges from V.sub.CC (typically ground) when transistor Q1 is turned off to approximately -0.35 V when Q1 is conducting the current I.sub.S (i.e., I.sub.S .times.R1=0.35 V).
A conventional buffered emitter-coupled logic (ECL) circuit 20 is illustrated in FIG. 2. To avoid transistor saturation and accommodate large voltage swings, as well as to increase the interconnect driving capabilities, emitter followers Q3 and Q4 have been added. The emitter followers Q3 and Q4 have their collectors connected to a separate positive supply voltage V.sub.CCA to ensure that any changes in load currents during switching do not cause a change in V.sub.CC through the small but finite inductance of the V.sub.CCA bond wire and package lead. Outside the package, the V.sub.CC and V.sub.CCA leads are normally connected to a common V.sub.CC distribution. Thus, the voltages at the emitters of emitter followers Q3 and Q4 are approximately one diode drop (.phi.) below the output voltages V.sub.C1 and V.sub.C2. Since R1=R2, I.sub.S .times.R1=I.sub.S .times.R2, which is equal to about 750 mV. Assuming that 750 mV.apprxeq..phi., the output voltages V'.sub.C1 and V'.sub.C2 vary between a high state of about -.phi. and a low state of about -2.phi..
FIGS. 1 and 2 show a single level of decision-making, represented by the conductive state of the transistor pair Q1 and Q2. A series of decision-making levels can be used to perform AND and NAND logic functions. FIG. 3 illustrates an AND/NAND logic gate 30, which includes an additional transistor pair consisting of transistors Q5 and Q6. Unless inputs A and B are both high, no current flows through load resistor R1, and a current flows through load resistor R2. If only input A is low, for example, current flows through transistors Q2 and Q5; if only input B is low, a current flows through transistor Q6. Hence, the output V.sub.C1 is equal to AB and the output V.sub.C2 is equal to AB.
In FIG. 3, assuming that V.sub.CC is set at ground, input A would vary between -.phi. (high) and -2.phi. (low) and reference voltage V.sub.BB would be set at approximately -1.5.phi.. Therefore, in the worst case, the coupled emitters of transistors Q1 and Q2 would be at approximately -2.5.phi.. The input B must be translated downwards by .phi., so that it varies between -2.phi. and -3.phi., and the reference voltage V'.sub.BB is set at about -2.5.phi..
The need to translate additional inputs downwards sets a limit on the number of decision-making levels that can be used in a series-gated ECL circuit. For a typical negative supply voltage V.sub.EE of -5.2 V, the practical limit known in the prior art is three levels. FIG. 4 illustrates a schematic circuit diagram of a generalized three-level ECL circuit 40, transistors Q7 and Q8 representing the third level. As shown, the coupled emitters of transistors Q5 and Q6 are at about -3.5.phi. and the additional input C is shifted downward by a transistor Q9 and a diode D1. Thus, input C is translated downward by 2.phi. so that the voltage at the base of transistor Q7 varies between -3.0.phi. (high) and -4.0.phi. (low). The third reference voltage V''.sub.BB is set at -3.5.phi..
FIG. 4 also illustrates that current source CS includes a transistor Q10 and a resistor RCS. The current I.sub.S is determined by an internally generated reference voltage V.sub.CS, the value of resistor RCS, and the base-emitter voltage of transistor Q10. V.sub.CS is designed to remain fixed with respect to the negative supply voltage V.sub.EE, which makes I.sub.S independent of supply voltage. Regulating the current I.sub.S in this way simplifies system design because the output voltage and switching parameters are not sensitive to changes in V.sub.EE. Output voltage levels are determined primarily by the voltage drops across load resistors R1 and R2 resulting from the collector currents of transistors Q1 and Q2. Since these collector currents are determined by I.sub.S and the .alpha.'s of transistors Q1 and Q2, the voltage drops across the load resistors R1 and R2 are relatively insensitive to variations in V.sub.EE.
Using a current source of this kind creates a voltage drop of approximately 1.5.phi. between the base of transistor Q10 and the negative supply voltage V.sub.EE. This is the result of the band gap regulator design. Since the collector of transistor Q10 is at a voltage approximately equal to -4.5.phi., the total voltage drop between the positive and negative supply rails is approximately 6.phi.. With a supply voltage of 5.2 V (V.sub.EE =-5.2 V.+-.5%), which is typical in 10 KH logic, this arrangement limits the number of decision-making levels that can be connected in a series-gated arrangement to a maximum of three.
Since the use of series-gated arrangements greatly enhances logic capability and performance with low device count, it is desirable to increase the permissible number of decision-making levels. This is accomplished in a circuit in accordance with the principles of this invention.